1. Field of the Invention
This invention relates to an image controlling apparatus which is used for a car navigation system, which sends data stored in the frame memory to a raster scan type display apparatus, and especially relates to an image display controlling apparatus which controls superimposing a plurality of images of the frames to display a desired image on the display screen.
2. Description of the Related Art
In a car navigation system, a display apparatus is used which displays a plurality of gradually scrolled maps on a fixed basic screen.
FIG. 10 shows a circuit diagram of an image controlling apparatus used for the above conventional display apparatus. Reference numeral 11 denotes a First In First Out (FIFO) memory for storing the image data of the first frame as the highest order frame, reference numeral 12 denotes a FIFO memory for storing the image data of the second frame, reference numeral 13 denotes a FIFO memory for storing the image data of the third frame, reference numeral 14 denotes a FIFO memory for storing the image data of the fourth frame as the lowest order frame. Reference numeral 15 denotes a memory previously storing color data indicating transparent and color data indicating a border for each frame in a frame hierarchy. Reference numerals 16 to 19 denote a comparator for comparing two pieces of data input from the input terminals A and B and for outputting a signal indicating equality from the terminal EQ. Reference numerals 20 to 23 each denote a switch selecting one of the two signals input from the input terminals A and B based on the signal input from controlling terminal S.
The memory 15 includes a region 15a storing transparent color data T1 indicating transparent in the first frame as a highest layer, a region 15b storing transparent color data T2 indicating transparent in the second frame, a region 15c storing transparent color data T3 indicating transparent in the third frame, a region 15d storing transparent color data T4 indicating transparency in the fourth frame and a region 15e storing a border color data BC indicating a color displayed at the pixel position where all the superimposed frames have transparent color data.
When the plurality of the frames are displayed by superimposing the frames on each other, it is judged whether the image data on a pixel in a frame is transparent color data or not. As a result of the judgement, the image data is selected when the data is not a transparent color data. On the other hand, when the data is a transparent color data, the data in a next lower layer frame is selected.
At first, image data in each frame is transferred to the FIFO memories 11, 12, 13 and 14. These image data includes color data indicating the combination of the colors of Red, Green and Blue (RGB) for a pixel. When a next lower frame to a certain frame is to be displayed by penetrating the certain frame, transparent color data should be written in the certain frame. Namely, in the certain frame, a color that the transparent color data indicates cannot be displayed. Transparent color data T1, T2, T3 and T4 are previously written in the regions 15a, 15b, 15c and 15d, respectively. Further, border color data BC is stored in the region 15e of the memory 15, which is used for display when all the frames have transparent data in a region where all the frames superimpose each other.
The image data of the first frame stored in the FIFO memory 11 is input to the image data input terminal A of the switch 23 and the image data input terminal A of the comparator 19 pixel by pixel. On the other hand, transparent color data T1 is input to the input terminal B of the comparator 19. Namely, when the image data input to the input terminal A of the comparator 19 is equal to the transparent color data T1, the comparator 19 outputs an "H" level signal from the output terminal EQ. This "H" level signal is input to the control input terminal S of the switch 23. The signal output from the output terminal Y of the switch 22 corresponding to the second frame is selected and output from the output terminal Y of the switch 23. On the other hand, when image data input to the input terminal A of the comparator 19 is not equal to the transparent color data T1, an "L" level signal is output from the output terminal EQ. This "L" level signal is input to the control input terminal S of the switch 23. Then, the image data of the first frame output from the FIFO memory 11 is selected and output from the output terminal Y of the switch 23, thereafter an image corresponding to the image data is displayed.
Operations performed for the second frame and third frame are similar to the operation for the first frame. Namely, when transparent color data in each frame is input to the FIFO memories 12 and 13, the switches 22 and 21 select and output the image data of the next lower frame. The fourth frame is the lowest frame and when the image data of the fourth frame stored in the FIFO memory 14 is equal to the transparent color data T4 for the fourth frame, the border color data BC is selected by the switch 20.
As explained above, the frame superimposing display is realized by judging pixel by pixel whether the image data of each frame is the transparent color data or not and by outputting image data from the switches 20 to 23 corresponding to the frames. Therefore, in order to display the area of a lower frame layer, it is necessary to write data to the FIFO memories 11 to 14 such that data in an area corresponding to the area of the lower frame layer is replaced with transparent color data. Namely, a large amount of accesses are generated for memory data replacement other than accesses for refreshing memory, thereby the image display speed is reduced.
When opening a window in a certain frame layer by writing transparent color data for displaying a lower frame data and when the certain frame layer is scrolled, data in the certain frame layer should be replaced as the layer is being scrolled, which requires replacement of a larger amount of data. This further affects the speed of displaying images.
FIG. 11 is a circuit diagram showing the structure of another conventional image display control apparatus. The same reference numerals are attached to the same portions of the image display control apparatus as those shown in FIG. 10. In FIG. 11, reference numeral 30 denotes a switch which selects one of the image data values output from FIFO memories 11 to 14 and the border color data value BC stored in the region 15e of the memory 15 based on the control signals input to the input terminals S0, S1, S2 and S3, reference numeral 31 denotes an arbiter which generates control signals to be input to the input terminals S0, S1, S2 and S3 based on the signals output from the output terminals EQ of the comparators 16 to 19.
In the image display control apparatus shown in FIG. 11, the image data of the frame layers output from FIFO memories 11 to 14 are input to the image data input terminals A0, A1, A2 and A3, as well as to the input terminals A of the comparators 16 to 19, respectively. In these comparators 16 to 19, image data of frame layers and transparent color data T1 to T4 are compared, respectively. If these pieces of data are identical, "H" level signals are output from terminals EQ of the comparators 16 to 19, respectively. The signals from terminals EQ of the comparators 16 to 19 are input to the input terminals A0, A1, A2 and A3. The arbiter 31 selects and outputs one of the image data values of each frame stored in the FIFO memories 11 to 14 and border color data value BC stored in the memory 15 based on the combination of the signals input to the input terminals A0, A1, A2 and A3.
For example, when image data values of the first frame, the second frame and the third frame output from FIFO memories 11 to 13 at a pixel position are transparent color data and when image data of the fourth frame is not transparent color data, the comparator 16 outputs a "L" level signal and comparators 17 to 19 output an "H" level signal from the terminal EQ. In this case, the arbiter 31 outputs signals from output terminals Y0, Y1, Y2 and Y3 to the S0, S1, S2 to S3 of the switch 30 such that the switch 30 selects image data output from FIFO memory 14.
In the image display controlling apparatus shown in FIG. 11, time delay of the image data output from the FIFO memory 14 in the image display control apparatus shown in FIG. 10 can be eliminated. However, in order to display a lower order frame, it is necessary to write data to the FIFO memory such that the data on the corresponding place of the higher order frame is replaced by the transparent color data, thereby display speed is lowered.